System Architecture Description

Revision History

1. Purpose

This document describes the system architecture of the foxBMS 2 POSIX port BMS. It decomposes the system into layers, tasks, and communication interfaces, satisfying ASPICE SYS.3 base practices and ISO 26262 Part 4 system design requirements.

2. Scope

The architecture covers the full BMS software stack from application-level algorithms down to the hardware abstraction layer, including the POSIX-specific adaptations.

3. References

4. System Context

The BMS manages a single battery string (18s1p) connected to a vehicle load via three contactors (string+, string-, precharge). External interfaces are:

• CAN bus to vehicle controller
• SPI bus to analog front end (AFE) for cell voltage and temperature measurement
• I2C bus to peripherals
• Current sensor (Isabellenhuette IVT) via CAN
• Interlock circuit for physical safety loop

5. System Block Diagram

+-------------------------------------------------------------------+
|                     APPLICATION LAYER                              |
|                                                                    |
|  +-------+  +-----+  +-----------+  +----------+  +----------+   |
|  |  BMS  |  | SOA |  | Algorithm |  | Balancing|  |Plausibil.|   |
|  | State |  |Check|  | (SOC/SOE) |  |          |  |          |   |
|  | Mach. |  |     |  |           |  |          |  |Redundancy|   |
|  +---+---+  +--+--+  +-----+-----+  +----+-----+  +----+-----+   |
|      |         |            |              |              |        |
+------+---------+------------+--------------+--------------+--------+
       |         |            |              |              |
+------+---------+------------+--------------+--------------+--------+
|                      ENGINE LAYER                                  |
|                                                                    |
|  +----------+       +-----------+       +----------+               |
|  | Database |       |   DIAG    |       |   SYS    |               |
|  | (R/W)    |       | Handler   |       |  State   |               |
|  +----+-----+       +-----+-----+       +----+-----+               |
|       |                   |                   |                    |
+-------+-------------------+-------------------+--------------------+
        |                   |                   |
+-------+-------------------+-------------------+--------------------+
|                      DRIVER LAYER                                  |
|                                                                    |
|  +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ +----+ |
|  | CAN | | SPI | | I2C | | SBC | | SPS | |Cont.| | IMD | |Intl| |
|  +--+--+ +--+--+ +--+--+ +--+--+ +--+--+ +--+--+ +--+--+ +-+--+ |
|     |       |       |       |       |       |       |       |     |
+-----+-------+-------+-------+-------+-------+-------+-------+-----+
      |       |       |       |       |       |       |       |
+-----+-------+-------+-------+-------+-------+-------+-------+-----+
|                 HARDWARE ABSTRACTION LAYER                         |
|                                                                    |
|             +-------------+  OR  +-------------+                   |
|             |   TMS570    |      |    POSIX    |                   |
|             | (hardware)  |      |   (stubs)   |                   |
|             +-------------+      +-------------+                   |
|                                                                    |
+-------------------------------------------------------------------+

6. Layer Descriptions

6.1 Application Layer

The Application layer implements the BMS functional logic. It is hardware-independent and operates exclusively through the Engine and Driver layer APIs.

6.2 Engine Layer

The Engine layer provides core services to the Application layer.

6.3 Driver Layer

The Driver layer abstracts hardware peripherals into software-callable interfaces.

6.4 Hardware Abstraction Layer

7. Task Architecture

7.1 FreeRTOS Tasks (Production Target)

7.2 POSIX Cooperative Loop (SIL Target)

The FreeRTOS scheduler is replaced by a single-threaded cooperative main loop that calls each task function in sequence. The loop executes in the order listed in Section 7.1, preserving the relative priority and data-flow dependencies.

main():
    SYSTEM_Init()
    while (running):
        ENGINE_Task()
        TASK_1ms()
        AFE_Task()
        TASK_10ms()
        TASK_100ms()
        I2C_Task()
        ALGO_100ms()
        usleep(1000)  // 1ms tick approximation

8. Data Flow

8.1 Measurement Path

AFE (SPI) --> AFE Driver --> Database[CELL_VOLTAGE] --> SOA --> DIAG --> BMS
AFE (SPI) --> AFE Driver --> Database[CELL_TEMPERATURE] --> SOA --> DIAG --> BMS
IVT (CAN) --> CAN Driver --> Database[CURRENT] --> SOA --> DIAG --> BMS

8.2 Safety Path

SOA check (threshold comparison)
    |
    v
DIAG_Handler (increment threshold counter)
    |
    v
Counter >= threshold? --> Yes --> Set FATAL flag
    |
    v
BMS state machine reads FATAL --> Transition to ERROR
    |
    v
ERROR state --> Open all contactors (string+, string-, precharge)

8.3 Command Path

Vehicle Controller --> CAN 0x210 (State Request)
    |
    v
CAN RX Handler --> Database[STATE_REQUEST]
    |
    v
BMS State Machine --> Evaluate transition
    |
    v
Contactor Driver --> Actuate contactors

9. CAN Interface Specification

9.1 Transmit Messages

9.2 Receive Messages

10. Safety Architecture Summary

The safety concept follows a defense-in-depth approach:

1. Layer 1 -- SOA: Continuous comparison of measurements against MOL/RSL/MSL.
2. Layer 2 -- DIAG: Debounced threshold counters prevent single-event false trips.
3. Layer 3 -- BMS: ERROR state latching with dual-condition exit (fault clear + explicit request).
4. Layer 4 -- Contactors: Physical disconnection of the battery string.

This architecture is preserved in the POSIX port for all software-checkable paths.

End of Document